2. Rabbit 3000 Design Features

The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly identical to the immediate predecessor processor, the Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a substantial number of new instructions. Some obsolete or redundant Z180 instructions have been dropped to make available efficient 1-byte opcodes for important new instructions. (see Chapter 20, "Differences Rabbit vs. Z80/Z180 Instructions,".) The advantage of this evolutionary approach is that users familiar with the Z80 or Z180 can immediately understand Rabbit assembly language. Existing Z80 or Z180 source code can be assembled or compiled for the Rabbit with minimal changes.

Changing technology has made some features of the Z80/Z180 family obsolete, and these features have been dropped in the Rabbit. For example, the Rabbit has no special support for dynamic RAM but it has extensive support for static memory. This is because the price of static memory has decreased to the point that it has become the preferred choice for medium-scale embedded systems. The Rabbit has no support for DMA (direct memory access) because most of the uses for which DMA is traditionally used do not apply to embedded systems, or they can be accomplished better in other ways, such as fast interrupt routines, external state machines or slave processors.

Our experience in writing C compilers has revealed the shortcomings of the Z80 instruction set for executing the C language. The main problem is the lack of instructions for handling 16-bit words and for accessing data at a computed address, especially when the stack contains that data. New instructions correct these problems.

Another problem with many 8-bit processors is their slow execution and a lack of number-crunching ability. Good floating-point arithmetic is an important productivity feature in smaller systems. It is easy to solve many programming problems if an adequate floating-point capability is available. The Rabbit's improved instruction set provides fast floating-point and fast integer math capabilities.

The Rabbit supports four levels of interrupt priorities. This is an important feature that allows the effective use of fast interrupt routines for real-time tasks.

2.1 The Rabbit 8-bit Processor vs. Other Processors

The Rabbit 3000 processor has been designed with the objective of creating practical systems to solve real world problems in an economical fashion. A cursory comparison of the Rabbit 3000 compared to other processors with similar capabilities may miss certain Rabbit strong points.

• The Rabbit is a processor that can be used to build a system in which EMI is nearly absent, even at clock frequencies in excess of 40 MHz. This is due to the split power supply, the clock doubler, the clock spectrum spreader and the PC board layout advice (or processor core modules) that we provide. Low EMI is a huge timesaver for the designer pressed to meet schedules and pass government EMI tests of the final product.

• Execution speed with the Rabbit is usually a pleasant surprise compared to other processors. This is due to the well-chosen and compact instruction set partnered with and excellent compiler and library. We have many benchmarks, comparing the Rabbit to 186, 386, 8051, Z180 and ez80 families of processors that prove the point.

• The Rabbit memory bus is an exceptionally efficient and very clean design. No external logic is required to support static memory chips. Battery-backed external memory is supported by built-in functionality. During reduced-power slow-clock operation the memory duty cycle can be correspondingly reduced using built-in hardware, resulting in low power consumption by the memories.

• The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles. This has many advantages compared to a single-clock design, and on closer examination the advantages of the single-clock system turn out to be mostly chimerical. The advantages include: easy design to avoid bus fights, clean write cycles with solid data and address hold times, flexibility to have memory output enable access times greater than ½ of the bus cycle, and the ability to use an asymmetric clock generated by a clock doubler. The supposed advantage that single-clock systems have of double-speed bus operation is not possible with real-world memories unless the memory is backed with fast-cache RAM.

• The Rabbit 3000 operates at 3.6 V or less, but it has 5 V tolerant inputs and has a second complete bus for I/O operations that is separate from the memory bus. This second auxiliary bus can be enabled by the application as a designer option. These features make it easy to design systems that mix 3 V and 5 V components, and avoid the loading problems and the EMI problems that result if the memory bus is extended to connect with many I/O devices.

• The Rabbit may be remotely programmed, including complete cold-boot, via a serial link, Ethernet, or even via a network or the Internet using built in capabilities and/or the RabbitLink ethernet network accessory device. These capabilities proven and inexpensive to implement.

• The Rabbit 3000 on-chip peripheral complement is huge compared to competitive processors.

The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a compact instruction set, its performance is as good as many 16-bit processors.

We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occasions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount of money. Many Rabbit instructions are 1 byte long. In contrast, the minimum instruction length on most 32-bit RISC processors is 32 bits.

2.2 Overview of On-Chip Peripherals and Features

The on-chip peripherals were chosen based on our experience as to what types of peripheral devices are most useful in small embedded systems. The major on-chip peripherals are the serial ports, system clock, time/date oscillator, parallel I/O, slave port, motion encoders, pulse width modulators, pulse measurement, and timers. These and other features are described below.

2.2.1 5 V Tolerant Inputs

The Rabbit 3000 operates on a voltage in the range of 1.8 V to 3.6 V, but most Rabbit 3000 input pins are 5 V tolerant. The exceptions are the power supply pins, and the oscillator buffer pins. When a 5 V signal is applied to 5 V tolerant pins, they present a high impedance even if the Rabbit power is off. (The inputs may be damaged at some voltage above 8 V.) The 5 V tolerant feature allows 5 V devices that have a suitable switching threshold to be directly connected to the Rabbit. This includes HCT family parts operated at 5 V that have an input threshold between 0.8 and 2 V.

NOTE

CMOS devices operated at 5 V that have a threshold at 2.5 V are not suitable for direct connection because the Rabbit outputs do not rise above VDD, which cannot exceed 3.6 V, and is often specified as 3.3 V. Although a CMOS input with a 2.5 V threshold may switch at 3.3 V, it will consume excessive current and switch slowly.

In order to translate between 5 V and 3.3 V, HCT family parts powered from 5 V can be used, and are often the best solution. There is also the "LVT" family of parts that operate from 2.0 V to 3.3 V, but that have 5 V tolerant inputs and are available from many suppliers. True level-translating parts are available with separate 3.3 V and 5 V supply pins, but these parts are not usually needed, and have design traps involving power sequencing. Many charge pump chips that perform DC to DC voltage conversion at low cost have been introduced in recent years. These are convenient for systems with dual voltage requirements.

2.2.2 Serial Ports

There are six serial ports designated ports A, B, C, D, E, and F. All six serial ports can operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8. The asynchronous ports use 7-bit or 8-bit data formats, with or without parity. A 9th bit address scheme, where an additional bit is set or cleared to mark the first byte of a message, is also supported.

The serial port software driver can tell when the last byte of a message has finished transmitting from the output shift register - correcting an important defect of the Z180. This is important for RS-485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent. In many UARTs, including those on the Z180, it is difficult to generate an interrupt after the last bit is sent. A so called address bit can be transmitted as either high or low after the last data bit. The address bit, if used, is followed by a high stop bit. This facility can be used to transmit 2 stop bits or a parity bit if desired. The ability to directly transmit a high voltage level address bit was not included in the original revision of the Rabbit 2000 processor.

Serial ports A, B, C and D can be operated in the clocked serial mode. In this mode, a clock line synchronously clocks the data in or out. Either the Rabbit serial port or the remote device can supply the clock. When the Rabbit provides the clock, the baud rate can be up to 1/2 of the system clock frequency. When the clock is provided by another device the maximum data rate is system clock divided by 6 due to the need to synchronize the externally supplied clock with the internal clock. The clocked serial mode may be used to support "SPI" bus devices.

Serial Port A has special features. It can be used to cold-boot the system after reset. Serial Port A is the normal port that is used for software development under Dynamic C.

All the serial ports have a special timing mode that supports infrared data communications standards.

2.2.3 System Clock

The main oscillator uses an external crystal with a frequency typically in the range from 1.8 MHz to 26 MHz. The processor clock is derived from the oscillator output by either doubling the frequency, using the frequency directly, or dividing the frequency by 2, 4, 6 or by 8. The processor clock can also be driven by the 32.768 kHz real-time clock oscillator for very low power operation, in which case the main oscillator can be shut down under software control.

2.2.4 32.768 kHz Oscillator Input

The 32.768 kHz oscillator input is designed to accept a 32.768 kHz clock. A suggested low-power clock circuit using "tiny logic" parts is documented and low in cost. The 32.768 kHz clock is used to drive a battery-backable (there is a separate power pin) internal 48-bit counter that serves as a real-time clock (RTC). The counter can be set and read by software and is intended for keeping the date and time. There are enough bits to keep the date for more than 100 years. The 32.768 kHz oscillator input is also used to drive the watchdog timer and to generate the baud clock for Serial Port A during the cold-boot sequence.

2.2.5 Parallel I/O

There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port lines have alternate functions, such as serial data or chip select strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs. The output registers are cascaded as shown in Figure 2-1.

Figure 2-1. Cascaded Output Registers for Parallel Ports D and E

Stores to the port are loaded in the first-level register. That register in turn is transferred to the output register on a selected timer clock. The clock can be selected to be the output of Timer A1, B1, B2 or the peripheral clock (divided by 2?). The timer signal can also cause an interrupt that can be used to set up the next bit to be output on the next timer pulse. This feature can be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time. Applications include communications signaling, pulse width modulation and driving stepper motors. (A separate pulse width modulation facility is also included in the Rabbit 3000.)

Figure 2-2. Digital Filtering Input Pins

Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2-2. This prevents pulses shorter then the peripheral clock from being recognized, synchronizes external pulses to the internal clock, and avoids problems with meta stability (temporarily indeterminate logical conditions due to marginal set up time with respect to the clock).

2.2.6 Slave Port

The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port. These same registers can be written as I/O registers by the Rabbit slave. Three additional registers transmit data in the opposite direction. They are written by the master by means of the two select lines and a write strobe.

Figure 2-3 shows the data paths in the slave port.

Figure 2-3. Slave-Port Data Paths

The slave Rabbit can read the same registers as I/O registers. When incoming data bits are written into one of the registers, status bits indicate which registers have been written, and an optional interrupt can be programmed to take place when the write occurs. When the slave writes to one of the registers carrying data bits outward, an attention line is enabled so that the master can detect the data change and be interrupted if desired. One line tells the master that the slave has read all the incoming data. Another line tells the master that new outgoing data bits are available and have not yet been read by the master. The slave port can be used to signal the master to perform tasks using a variety of communication protocols over the slave port.

2.2.7 Auxiliary I/O Bus

The Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditional microprocessor design the same address and data lines are used for both memory and I/O spaces. Sharing address and data lines in this manner often forces compromises or makes design more complicated. Generally the memory bus has more critical timing and less tolerant of additional capacitive loading imposed by sharing it with an I/O bus.

With the Rabbit 3000, the designer has the option of enabling completely separate buses for I/O and memory. The auxiliary I/O bus uses many of the same pins used by the slave port, so its operation is mutually exclusive from operation of the slave port. Parallel Port A is used to provide 8 bidirectional data lines. Parallel Port B bits 2:7 provide 6 address lines, the least significant 6 lines of the 16 lines that define the full I/O space. The auxiliary bus is only active on I/O bus cycles. The address lines remain in the same state assumed at the end of the previous I/O cycle until another I/O cycle takes place. I/O chip selects as well as read and write strobes are available at various other pins so that the 64 byte space defined by the 6 address lines may be easily expanded. I/O cycles also execute in parallel on the main (memory) bus when they take place on the auxiliary bus, so additional address lines can be buffered and provided if needed.

By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of the capacitive load that would otherwise slow the memory. For core modules based on the Rabbit 3000, fewer pins are required to exit the core module since the slave port and the I/O bus can share the same pins and the memory bus no longer needs to exit the module to provide I/O capability. Because the I/O bus has less activity and is slower than the memory bus, it can be run further physically without EMI and ground bounce problems. 5 V signals can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected.

2.2.8 Timers

The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz oscillator divided by 16, giving an interrupt every 488 µs if enabled. This is intended to be used as a general-purpose clock interrupt. Timer A consists of ten 8-bit countdown and reload registers that can be cascaded up to two levels deep. Each countdown register can be set to divide by any number between 1 and 256. The output of six of the timers is used to provide baud clocks for the serial ports. Any of these registers can also cause interrupts and clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit counter that can be read but not written. There are two 10-bit match registers and comparators. If the match register matches the counter, a pulse is output. Thus the timer can be programmed to output a pulse at a predetermined count in the future. This pulse can be used to clock the timer-synchronized parallel-port output registers as well as cause an interrupt. Timer B is convenient for creating an event at a precise time in the future under program control.

Figure 2-4 illustrates the Rabbit timers.

Figure 2-4. Rabbit Timers A and B

2.2.9 Input Capture Channels

The input capture channels are used to determine the time at which an event takes place. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16 input pins that can be selected as input for either of the two channels. A 16 bit counter is used to record the time at which the event takes place. The counter is driven by the output of Timer A8 and can be set to count at a rate ranging from full clock speed to 1/256 the clock speed.

Two events are recognized: a start condition and a stop condition. The start condition may be used to start counting and the stop condition to stop counting. However the counter may also run continuously or run until a stop condition is encountered. The start and stop conditions may also be used to latch the current time at the instant the condition occurs rather than actually start or stop the counter. The same pin may be used to detect the start and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However, optionally, the start and stop condition can be input from separate pins.

The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse. In this case the maximum error in the measurement is approximately 2 periods of the clock used to count the counter. If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions or both and cause an interrupt each time the count is captured. In this case the start and stop conditions lose the connection with starting or stopping the counter and simply become capture conditions that may be specified for 2 independent edge detectors. The counter can also be cleared and started under software control and then have its value captured in response to an input.

If desired the capture counter can synchronized with Timer B outputs used to synchronously load parallel port output registers. This makes it possible to generate an output signal precisely synchronized with an input signal. Usually it will be desired to synchronize one of the input capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a precise time using Timer B to set the output time and capturing the same pulse. Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured, provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B. The minimum time delay needed is probably less than 10 microseconds if the software is done carefully the clock speed is reasonably high.

2.2.10 Quadrature Encoder Inputs

A quadrature encoder is a common electromechanical device used to track the rotation of a shaft, or in some cases to track the motion of a linear follower. These devices are usually implemented by the use of a disk or a strip with alternate opaque and transparent bands that excite dual optical detectors. The output signals are square waves 90 degrees out of phase also called being in quadrature with each other. By having quadrature signals, the direction of rotation can be detected by noting which signal leads the other signal.

The Rabbit 3000 has 2 quadrature encoder units. Each unit has 2 inputs, one being the normal input and the other the 90 degree or quadrature input. An 8 bit up down counter counts encoder steps in the forward and backward direction. The count can be extended beyond 8 bits by an interrupt that takes place each time the count overflows or underflows. The external signals are synchronized with an internal clock provided by the output of Timer A10.

2.2.11 Pulse Width Modulation Outputs

The pulse width modulated output generates a train of pulses periodic on a 1024 pulse frame with a duty cycle that varies from 1/1024 to 1024/1024. There are 4 independent PWM units. The units are driven by the output of Timer A9 which may be used to vary the length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into groups distributed 256 counts apart in the 1024 frame. The pulse width modulation outputs can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be used to directly drive devices that have intrinsic filtering such as motors or solenoids.

2.2.12 Spread Spectrum Clock

The main system clock, which is generated by the crystal oscillator or input from an external oscillator, can be modified by a clock spectrum spreader internal to the Rabbit 3000 chip. When the spectrum spreader is engaged, the clock is alternately speeded up and slowed down, thus spreading the spectrum of the clock harmonics in the frequency domain. This reduces EMI and improves the results of official radiated-emissions tests typically by 15-20 dB at critical frequencies. The spectrum spreader has 3 modes of operation: off, normal, and strong. Slightly faster memory access time is required when the spectrum spreader is used: 2-3 ns for the normal setting when the clock doubler is enabled, and 6-9 ns for the strong setting when the clock doubler is used. The spreader slightly influences baud rates and other timings because it introduces clock jitter, but the effect is usually small enough to be negligible.

2.2.13 Separate Core and I/O Power Pins

The silicon die that constitutes the Rabbit 3000 processor is divided into the core logic and the I/O ring. The I/O ring located on the 4 edges of the die holds the bonding pads and the large transistors used to create the I/O buffers that drive signals to the external world. The core section, inside the I/O ring contains the main processor and peripheral logic. The clock and clock edges in the core are very fast with large transient currents that create a lot of noise that is communicated to the outside of the package via the power pins. The I/O buffers have slower switching times and mostly operate at much lower frequencies than the core logic. The Rabbit has separate power and ground pins for the core and I/O ring. This allows the designer to feed clean power to the I/O ring filtered to be free of the noise generated by the core switching. This minimizes high frequency noise that would otherwise appear on output pins driven by buffers in the I/O ring. The result is lower EMI.

2.3 Design Standards

The same functionality can often be accomplished in more than one way with the Rabbit 3000. By publishing design standards, or standard ways to accomplish common objectives, software and hardware support become easier.

Refer to the Rabbit 3000 Microprocessor Designer's Handbook for additional information.

2.3.1 Programming Port

Rabbit Semiconductor publishes a specification for a standard programming port (see Appendix A.1, "The Rabbit Programming Port") and provides a converter cable that may be used to connect a PC serial port to the standard programming interface. The interface is implemented using a 10-pin connector with two rows of pins on 2 mm centers. The port is connected to Rabbit Serial Port A, to the startup mode pins on the Rabbit, to the Rabbit reset pin, and to a programmable output pin that is used to signal the PC that attention is needed. With proper precautions in design and software, it is possible to use Serial Port A as both a programming port and as a user-defined serial port, although this will not be necessary in most cases.

Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field.

2.3.2 Standard BIOS

Rabbit Semiconductor provides a standard BIOS for the Rabbit. The BIOS is a software program that manages startup and shutdown, and provides basic services for software running on the Rabbit.

2.4 Dynamic C Support for the Rabbit

Dynamic C is Z-World's interactive C language development system. Dynamic C runs on a PC under Windows 32-bit operating systems. Dynamic C provides a combined compiler, editor, and debugger. The usual method for debugging a target system based on the Rabbit is to implement the 10-pin programming connector that connects to the PC serial port via a standard converter cable. Dynamic C libraries contain highly perfected software to control the Rabbit. These includes drivers, utility and math routines and the debugging BIOS for Dynamic C.

In addition, the internationally known real-time operating system, uC/OS-II, has been ported to the Rabbit, and is available with Dynamic C Premier on a license-free, royalty-free basis for use in Rabbit-based products..