Rabbit 3000 Microprocessor
User's Manual
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12. Rabbit Serial Ports

The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can perform asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC synchronous communications in addition to standard asynchronous communications. Port A has the special capability of being used to remote boot the microprocessor via asynchronous, synchronous, or IrDA (asynchronous serial).

Table 12-1 lists the synchronous serial port signals.


Figure 12-1 shows a block diagram of the serial ports.


Figure 12-1. Block Diagram of Rabbit Serial Ports

The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th" bit or address bit mode of operation is also supported. The "9th" bit can be set high or low by accessing the appropriate serial port register. Although Parity and multiple stop bits are not directly supported by the hardware, the "9th" bit can be used to issue an extra stop bit (9th-bit high) or toggled to indicate parity.

12.1 Serial Port Register Layout

Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmission. The least significant bit (LSB) is always transmitted first. This is true for both asycnchronous and synchronous communication. If the write is performed to an alternate data register address, the extra address bit or 9th bit (8th bit if 7 data bits) is sent. When data bits have been received, they are read from the data register (LSB first). The control register is used to set the transmit and receive parameters. The status register may be tested to check on the operation of the serial port.


Figure 12-2. Functional Block Diagram of a Serial Port

The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. Timers A2-A7 supply the input clock for Serial Ports A-F. These timers can divide the frequency by any number from 1 to 256 (see Chapter 11). The input frequency to the timers can be selected in different ways described in the documentation for the timers. One choice is the peripheral clock--with that choice and a well-chosen crystal frequency for the main oscillator, the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer A0 at the highest Rabbit clock frequencies (see Section A.4 in Appendix A).

12.2 Serial Port Registers

Each serial port has 6 registers shown in the tables below. The status, control and extended registers may have somewhat different formats for different serial ports.












12.3 Serial Port Interrupt

A common interrupt vector is used for the receive and transmit interrupts. There is a separate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3. When an interrupt is requested, it will take place immediately when priorities allow and an instruction execution is complete. The interrupt is lost if the request flip-flop is cleared before the interrupt takes place. If the flip-flop is not cleared in the interrupt, another interrupt will take place when priorities are lowered.


Figure 12-3. Generation of Serial Port Interrupts

The receive interrupt request flip-flop is set after the stop bit is sampled on receive, nominally 1/2 of the way through the stop bit. Data bits are transferred on this same clock from the receive shift register to the receive data register.

The transmit interrupt request flip-flop is set on the leading edge of the start bit for data register empty and at the trailing edge of the stop bit for shift register empty (transmitter idle). Unless the data register is empty on this trailing edge of the stop bit, the transmitter does not become idle. The transmitter becomes idle only if the data register is empty at the trailing edge of the stop bit.

The serial port interrupt vectors are shown in Table 6-1.

12.4 Transmit Serial Data Timing

On transmit, if the interrupts are enabled, an interrupt is requested when the transmit register becomes empty and, in addition, an interrupt occurs when the shift register and transmit register both become empty, that is, when the transmitter becomes idle. The shift register is empty when the last bit is shifted out. When the transmit data register contains data and the shift register finishes sending data, the data bits are clocked from the transmit register to the shift register, and the shift register is never idle. The interrupt request is cleared either by writing to the data register or by writing to the status register (which does not affect the status register). The data register normally is clocked into the shift register each time the shift register finishes sending data, leaving the data register empty. This causes an interrupt request. The interrupt routine normally answers the interrupt before the shift register runs dry (9 to 11 baud clocks, depending on the mode of operation). The interrupt routine stores the next data item in the data register, clearing the interrupt request and supplying the next data bits to be sent. When all the characters have been sent, the interrupt service routine answers the interrupt once the data register becomes empty. Since it has no more data, it clears the interrupt request by storing to the status register. At this point the routine should check if the shift register is empty; normally it won't be. If it is, because the interrupt was answered late, the interrupt routine should do any final cleanup and store to the status register again in case the shift register became empty after the pending interrupt is cleared. Normally, though, the interrupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers, as in the case for RS-485 transmission.

12.5 Receive Serial Data Timing

When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register. After 7 or 8 data bits have been received, the next bit will be either a 9th (8th) address bit, or a stop bit will be sampled. If the Rx line is low, it is an address bit and the address bit received bit in the status register will be enabled. If an address bit is detected, the receiver will attempt to sample the stop bit. If the line is high when sampled, it is a stop bit and a new scan for a new start bit will begin after the sample point. At the same time, the data bits are transferred into the receive data register and an interrupt, if enabled, is requested.

On receive, an interrupt is requested when the receiver data register has data. This happens when data bits are transferred from the receive shift register to the data register. This also sets bit 7 of the status register. The interrupt request and bit 7 are cleared when the data register is read.

An interrupt is requested if bit 7 is high. The interrupt is requested on the edge of the transmitter data register becoming empty or the transmitter shift register becoming empty. The transmitter interrupt is cleared by writing to the status register or to the data register.

On receive, the scan for the next start bit starts immediately after the stop bit is detected. The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit.

The serial clock can be configured to be either 16× the data rate or 8× the data rate.


Figure 12-4. Serial Port Synchronization

12.6 Clocked Serial Ports

Ports A-D can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received first. By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock. The serial port can generate the clock or the clock can be provided externally.

The clock polarity is programmable in clocked serial mode according to Figure . The clocked serial transfer may also be synchronized to the output of either of the match conditions in Timer B to give precisely timed transfers.

To enable the clocked serial mode, a code must be in bits (3,2) of the control register, enabling the clocked serial mode with either an internal clock or an external clock. The transition between the external and the internal clock should be performed with care. Normally a pullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock.


Figure 12-5. Clock Polarities Supported in Clocked Serial Mode

In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications. However, to initiate basic sending or receiving, a command must be issued by writing to bits (7,6) of the control register for each byte sent or received. One command is for sending a byte, a different command is for receiving a byte, and yet another command can initiate a transmit and receive at the same time for full duplex communication. Alternatively, a read or write to the Serial Ports A-D Address registers (SxAR) eliminates the need to issue separate receive and transmit commands. In clocked serial mode, reading the data from the corresponding SxAR register automatically causes the receiver to start a byte receive operation, eliminating the need for software to issue the Start Receive command. Any data contained in the receive buffer will be read first before being replaced with new incoming data. Similarly, writing the data to the SxAR register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock.

To transmit in internal clock mode, the user must first load the data register (which must be empty) and then store the send code. When the shift register finishes sending the current character, if any, the data register will be loaded into the shift register and transmitted by an 8-clock burst. One character can be in the process of transmitting while another character is waiting in the data register tagged with the send code. The send code is effectively double-buffered.

To receive a character in internal clock mode, the receive shift register should be idle. The user then stores the receive code in the control register. A burst of 8 clocks will be generated and the sender must detect the clocks and shift output data to the data line on the falling edge of each clock. The receiver will sample the data on the rising edge of each clock for clock modes 00 and 01 or the falling edge for clock modes 10 and 11. The receive mode cannot double-buffer characters when using the internal clock. The shift register must be idle before another character receive can be initiated. However, the interrupt request and character ready takes place on the rising edge of the last clock pulse. If the next receive code is stored before the natural location of the next falling edge, another receive will be initiated without pausing the clock. To do this, the interrupt has to be serviced within 1/2 clock.

To transmit each byte in external clock mode, the user