Pin
name (Pin number) | Type | Function |
CLK (1) | out | May
be programmed to be Fcpu, Fcpu/2, or a general-purpose output. Fcpu is the main
processor clock, which in turn is programmed to be 2f, f, f/4, or f/8 (where f
is the frequency of the main system oscillator XTALB1/XTALB2). |
-RESET (37) | in | Master
reset. |
XTALB1 (90) XTALB2 (91) | I/O | Connections
for the main system oscillator quartz crystal. To use an external oscillator,
connect it to XTALB1 leaving XTALB2 unconnected. |
XTALA1
(40) XTALA2 (41) | I/O | Connections
for the 32.678 kHz quartz crystal. To use an external oscillator, connect it to
XTALA1 leaving XTALA2 unconnected. |
A0-A19
(7, 17-20, 61-68, 70-75, 79) | out | Address
bus |
D0-D7 (9-16) | I/O | Data
bus |
-WDTOUT (34) | out | Watchdog
timer output. Pulses low for 30µs when the timer expires. |
STATUS
(38) | out | May
be programmed as a general-purpose output or to indicate (when low) either an
opcode fetch cycle or an interrupt acknowledge cycle. |
SMODE0
(36) SMODE1 (35) | in | SMODE1
SMODE0 Startup mode
0 0 Start executing at address zero
0 1 Cold boot from
slave port
1 0 Cold boot from serial port A (clocked)
1 1 Cold boot form
serial port A (async, 2400 baud)
After booting these pins may be used as general-purpose
inputs |
-CS0 (8) -OE0 (6) -WE0 (69) | out | Normally
this chip select, output enable, and write enable are used to select the base
flash memory that holds the program code. |
-CS1
(5) -OE1 (76) -WE1 (80) | out | Normally
this chip select, output enable, and write enable are used to select a static
RAM. Two selection modes are provided to allow optimizing speed or power consumption. |
-CS2 (4) | out | A
general-purpose memory decode |
-BUFFEN
(33) | out | I/O
Buffer Enable. Active during an external I/O cycle. Saves power by allowing the
bus buffer to be enabled only when needed. |
-IORD
(32) -IOWR (31) | out | I/O
read and write strobes. Active only during an I/O cycle. |
PA0-PA7
(81-88) | I/O | I/O
port A. General-purpose I/O or slave port data. Configured as inputs on reset. |
PB0-PB7 (93-100) | I/O | I/O
port B. General-purpose I/O, slave port control, serial port clocks. Details. |
PC0-PC7 (51, 52, 54-60) | I/O | I/O
port C. General-purpose I/O or serial data. Details. |
PD0-PD7
(43-50) | I/O | I/O
port D. General-purpose I/O (Open drain or active pull-up). Details. |
PE0-PE7 (21-30) | I/O | I/O
port E. General-purpose I/O or I/O strobes or external interrupts. Details. |
VBAT (42) | pwr | Supplies
power to the real-time clock (25uA at 2.3V). The clock may still run with the
rest of the processor powered down. |
VDD
(3, 28, 53, 78, 92) | pwr | 2.7
to 5.0 volts. (See power consumption table above) |
VSS
(2, 27, 39, 52, 77, 89) | pwr | Ground |
